1. Field of the Invention
The present invention generally relates to computer hardware and, more specifically, to a technique for optimizing the phase of a data signal transmitted across a communication link.
2. Description of the Related Art
A modern computer chip, such as a central processing unit (CPU) or a parallel processing unit (PPU), usually includes multiple chip components configured to communicate with one another via a communication link. For example, a given chip component could include a transmitter configured to transmit data signals across the communication link to a receiver included within another chip component. A conventional receiver oftentimes implements clock data recovery (CDR) hardware in order to recover timing information from a data signal received from a transmitter across the communication link. With the recovered timing information, the receiver is capable of sampling the received data signal at precise intervals via a sampling clock, and may thus re-create the original, transmitted signal.
When implementing CDR in this fashion, the transmitter usually performs an initial training routine with the receiver in order to calibrate the CDR hardware associated with the receiver and establish CDR lock on the received data signal. The CDR hardware may then continuously optimize the sampling clock phase in order to maintain CDR lock after the initial training routine. Such continuous optimization is required because the phase of the received data signal may vary over time (e.g., due to physical fluctuations associated with the transmitter and/or the communication link itself), and so the CDR hardware must adjust the phase of the sampling clock in order to track those phase variations.
The CDR-based approach discussed above may also be implemented with bi-directional communication links that allow data to be transmitted in either direction between chip components. For example, a transceiver within a given chip component could be configured to transmit data signals to or receive data signals from another transceiver within another chip component across a bi-directional communication link. In this situation, each chip component could include CDR hardware configured to recreate timing information associated with a received data signal. Each chip component could also perform the initial training routine discussed above in order to establish CDR lock with a corresponding received data signal, and then continuously optimize the sampling clock phase to maintain that CDR lock. This approach is well suited for transceivers that receive data signals frequently, because such transceivers are able to continuously optimize the sampling clock phase and, thus, maintain CDR lock.
However, transceivers that receive data signals infrequently cannot continuously optimize the sampling clock phase, and, thus, cannot maintain CDR lock. When a given transceiver loses CDR lock, that transceiver must perform the training routine again in order to calibrate the CDR hardware and regain CDR lock. This situation is problematic because the training routine may require a significant amount of time to perform, and the communication link cannot transport any useful data during that period of time. Moreover, performing the training routine requires excess power, and so the overall power requirements of the communication link and/or associated transceivers is increased.
Accordingly, what is needed in the art is a more effective technique for maintaining CDR lock in a communication link.